LE242: Digital Circuit Design


Course Information

Description: This course introduces the design and implemenatation of digital circuits. Topics include number representations, codes, Boolean algebra, logic gates, combinational and sequential circuit design (both synchronous and asynchronous). The real implementations begin with basic gates and progress to Programmable Logic Devices (PLD).

Course Instructor and contact information:

Instructor: Dr. Songyot Nakariyakul
E-mail: nsongyot@engr.tu.ac.th
Office: Room 420-2 Research Building
Office Hours: By appointment

Pre-requisites: None.

Problem sets: You are encouraged to do problem sets to reinforce what you learn in lecture, but they will not be graded.

Grading: Your grade in this course will be based principly on in-class exercises and exams.

Attendance 5%
Exercises 20%
Midterm exam 35%
Final exam 40%

Software: I will use Logisim (download) to simulate circuits in this course. Logisim is a freeware and it is easy to use.

Textbooks & Materials:

  1. Morris Mano and Micheal Ciletti, Digital Design, 4th ed, Prentice Hall, 2007
  2. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logics with Verilog Design, 3rd ed, McGraw-Hill, 2013 (optional)
  3. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logics with VHDL Design, 3rd ed, McGraw-Hill, 2008 (optional)
  4. Songyot Nakariyakul, Digital Circuit Analysis and Design, Danex Corporation Publishing, 2009. (in Thai)


  Topic Reading Lecture Notes Problem Set Solution
  Syllabus   pdf
  Introduction   slides
I Number systems M&C chaps 1.1-1.7 slides PS1 Sol1
II Boolean algebra M&C chaps 2, 3.7-3.9 slides PS2 Sol2
III Karnaugh map M&C chaps 3.1-3.6 slides PS3 Sol3
IV Design problem M&C chaps 4.1-4.4 slides    
V Combinational circuits I M&C chaps 4.9-4.11 slides PS4 Sol4
VI Combinational circuits II M&C chaps 4.5 -4.7 slides  
VII PLD B&V chaps 3.5-3.6 slides
VIII Latches and flip-flops M&C chaps 5.3-5.4 slides  
IX Synchronous sequential circuits M&C chaps 5.5-5.8 slides PS5 Sol5
X Registers and counters M&C chap 6 slides PS6 Sol6
XI Asynchronous sequential circuits B&V chaps 9.1-9.3 slides PS7 Sol7
XII Hazards B&V chaps 9.4, 9.6 slides